1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a semiconductor device provided with a universal logic cell (ULC), and a method of manufacturing the semiconductor device.
2. Description of the Related Art
A semiconductor device using a universal logic cell (ULC) and capable of switching at a high speed has been developed.
A “semi-custom technique” is known as a method of designing and manufacturing a semiconductor device by using a universal logic cell and a universal logic module. The semi-custom technique includes a “master slice method”.
According to the master slice method, for example, a universal logic module is formed beforehand in a master slice (base layer), which is known as a structured ASIC (Application Specific Integrated Circuit). The universal logic module is configured to be able to provide a logic gate such as a NAND circuit and a NOR circuit. Also, the universal logic modules are arranged in a matrix form on a chip.
According to the master slice method, a variety of universal logic modules are formed beforehand on a chip as a master slice (base layer). A power supply interconnection and a ground interconnection which are connected with transistors included in the universal logic modules are previously formed in a wiring layer of the base layer. In the wiring process, interconnections are formed in a customize layer on the master slice in accordance with the customer's requirement. As a result, a desired integrated circuit is realized and obtained.
Since the master slice is used in common and only the interconnections in the customize layer are customized, it is possible to manufacture a large variety of integrated circuits for a short period and at low cost. Also, a large variety of logic circuits can be manufactured by combining a plurality kinds of universal logic modules.
Japanese Unexamined Patent Publication JP-2002-198801 discloses such a universal logic module capable of switching at a high speed as described above and a cell using the universal logic module.
FIG. 1 shows a configuration of a cell according to the conventional technique. The cell includes a first universal logic module X, a second universal logic module Y, and a third universal logic module Z. Shown in FIG. 1 is a case where two first universal logic modules X, two second universal logic modules Y, and one third universal logic module Z are used. The number of each universal logic module is arbitrary. It is preferable that a cell includes the first universal logic module X, the second universal logic module Y and the third universal logic module Z at a ratio of 2:2:1.
FIG. 2 is a circuit diagram showing a configuration of the first universal logic module X as a component of the cell according to the above-mentioned conventional invention. The universal logic module is constituted by an inverted output type two-input multiplexer of which the first stage consists of inverters and the second stage consists of transfer gates. The universal logic module includes six nodes (a first node T1, a second node T2, a third node T3, a fourth node T4, a fifth node T5, and a sixth node T6), and five logic elements (a first inverter 10, a second inverter 11, a third inverter 12, a first transfer gate 20, and a second transfer gate 21).
For example, each of the first to the third inverters 10 to 12 has a well-known configuration where an N-channel MOS transistor and a P-channel MOS transistor are serially connected between a power supply and a ground (CMOS inverter). Each inverter inverts an inputted signal and outputs the inverted signal.
Each of the first and the second transfer gates (transmission gates) 20 and 21 has a configuration wherein an N-channel MOS transistor and a P-channel MOS transistor are connected in parallel. Each of the transfer gates transmits a signal supplied to an input terminal or prevents the passage of the signal supplied to the input terminal according to signals supplied to a gate of the N-channel MOS transistor and a gate of the P-channel MOS transistor. Hereinafter, the gate of the P-channel MOS transistor in the transfer gate is called a first control input terminal, and the gate of the N-channel MOS transistor in the transfer gate is called a second control input terminal.
The first node T1 is connected to an input terminal of the first inverter 10. An output terminal of the first inverter 10 is connected to the input terminal of the first transfer gate 20 and the second node T2.
The third node T3 is connected to an input terminal of the second inverter 11. An output terminal of the second inverter 11 is connected to the input terminal of the second transfer gate 21 and the sixth node T6.
The fourth node T4 is connected to an input terminal of the third inverter 12, the first control input terminal of the first transfer gate 20, and the second control input terminal of the second transfer gate 21. An output terminal of the third inverter 12 is connected to the second control input terminal of the first transfer gate 20, and the first control input terminal of the second transfer gate 21.
An output terminal of the first transfer gate 20 and an output terminal of the second transfer gate 21 are connected to the fifth node T5.
A basic operation of the universal logic module configured as described above will be explained. When a signal of a low level (hereinafter, to be referred to as “L level”) is inputted to the fourth node T4, both the P-channel MOS transistor and the N-channel MOS transistor in the first transfer gate 20 are turned ON, and both the P-channel MOS transistor and the N-channel MOS transistor in the second transfer gate 21 are turned OFF. As a result, a signal inputted from the first node T1 is inverted by the first inverter 10, and is outputted from the fifth node T5 through the first transfer gate 20.
On the other hand, when a signal of a high level (hereinafter, to be referred to as “H level”) is inputted to the fourth node T4, both the P-channel MOS transistor and the N-channel MOS transistor in the first transfer gate 20 are turned OFF, and both the P-channel MOS transistor and the N-channel MOS transistor in the second transfer gate 21 are turned ON. As a result, a signal inputted from the third node T3 is inverted by the second inverter 11, and is outputted from the fifth node T5 through the second transfer gate 21.
As described above, either the signal inputted into the first node T1 or the signal inputted into the third node T3 is inverted and outputted from the fifth node T5 according to the level of the signal supplied to the fourth node T4. In other words, a function of an “inverted output type multiplexer” is realized.
Next, a “NAND” circuit and a “NOR” circuit realized (provided) by the above-mentioned universal logic module will be explained.
FIG. 3A is a circuit diagram showing a configuration of a NAND circuit provided by using the universal logic module shown in FIG. 2.
As shown in FIG. 3A, the first node T1 of the universal logic module shown in FIG. 2 is connected to an L level (logic “0”), and the second node T2 and the sixth node T6 are not connected (denoted by NC). Also, the third node T3 and the fourth node T4 are used as input terminals (A, B), and the fifth node T5 is used as an output terminal (O). Thus, a two-input NAND circuit is realized. FIG. 3B is a connection diagram at the time of actually operating the NAND circuit shown in FIG. 3A. The first node T1 is connected to a ground line 7 so that the first node T1 is set to the L level (logic “0”).
According to the NAND circuit of the conventional technique, when the first transfer gate 20 is opened and the H level signal is driven from the fifth node T5, the driving capability is limited due to an ON resistance of the P-channel transistor in the first inverter 10.
It should be noted that the basic universal logic module (X) is formed in the base layer. A ground line 7 connected to the first node, and signal input lines connected to the nodes T3 and T4 are respectively formed in the customize layer, and are electrically connected to the corresponding node. The circuits shown in FIGS. 3A and 3B are described by a symbol of a “NAND” type (CMOS) shown in FIG. 3C.
FIG. 4A is a circuit diagram showing a configuration of a NOR circuit provided by using the universal logic module shown in FIG. 2.
As shown in FIG. 4A, the third node T3 of the universal logic module shown in FIG. 2 is connected to an H level (logic “1”), and the second node T2 and the sixth node T6 are not connected. Also, the first node T1 and the fourth node T4 are used as input terminals (A, B), and the fifth node T5 is used as an output terminal (O). Thus, a two-input NOR circuit is realized. FIG. 4B is a connection diagram at the time of actually operating the NOR circuit shown in FIG. 4A. The third node T3 is clamped to a power supply line 8 so that the third node T3 is set to the H level (logic “1”).
According to the NOR circuit of the conventional technique, when the second transfer gate 21 is opened and the L level signal is driven from the fifth node T5, the driving capability is limited due to an ON resistance of the N-channel transistor in the second inverter 11.
It should be noted that the basic universal logic module (X) is formed in the base layer. A power supply line 8 connected to the third node, and signal input lines connected to the nodes T1 and T4 are respectively formed in the customize layer, and are electrically connected to the corresponding node. The circuits shown in FIGS. 4A and 4B are described by a symbol of a “NOR” type (CMOS) shown in FIG. 4C.
According to the conventional technique, as described above, since the input of the inverter is connected to the power supply or the ground, the output driving capability of the universal logic module is limited due to the ON resistance of the P-channel transistor or the N-channel transistor in the inverter.